1. Field of the Invention
The present invention relates to a lead frame, a semiconductor device, and a method of manufacturing the semiconductor device.
2. Description of the Related Art
FIG. 7 is a cross-sectional view illustrating a manufacturing method for a related art semiconductor device. FIG. 7 shows a state in which resin encapsulation is performed while a lead frame 104 mounted with a semiconductor chip 102 is disposed in a die 106. The lead frame 104 includes an island 108, hanger pins 110, and lead terminals 112. The lead terminals 112 are electrically connected with a semiconductor chip 102 by wire bonding. Further, in order to obtain a semiconductor device having a structure in which the island 108 having a function serving as a radiation plate is exposed to a sealing resin, a lead frame 104 is disposed so that a lower surface of the island 108 is brought into contact with a bottom surface of the die 106.
However, as shown in FIG. 7, there may occur a case where the island 108 is inclined due to a force of flow when the sealing resin is injected into the die 106. Then, as shown in FIG. 8, the resin enters below the island 108 to produce an unfavorable resin burr 114 on the lower surface of the island 108. As a result, only a part of the lower surface of the island 108 can be exposed to the surface of the sealing resin 116. FIG. 8 is a plan view showing a back surface of a semiconductor device after the fabrication thereof. Heat conductivity of the resin burr 114 is lower than that, of the island 108 formed of steel, etc. For that reason, a heat radiation effect becomes lower, resulting in raising an operation temperature of the semiconductor chip 102. This causes a malfunction or a failure of the semiconductor chip 102.
FIG. 9 is a cross-sectional view illustrating a method of manufacturing a semiconductor device disclosed in Japanese Patent Application Laid-Open No. Hei 10-209194. In FIG. 9 a lead frame 206 including an island 202 and lead terminals 204 is disposed in a die 208. Mounted on the island 202 is a semiconductor chip 210. The semiconductor chip 210 is electrically connected to the lead terminals 204 by wire bonding. The die 208 has a suction hole 212 formed at a portion contacting the island 202. Using a suction force through the suction hole 212, the island 202 is fixed to a bottom surface of the die 208.
However, in the manufacturing method disclosed in Japanese Patent Application Laid-Open No. Hei 10-209194, formation of the suction hole in the die is required, resulting in increasing processing cost for the die.